Daniel Ferreto

Daniel Ferreto Chavarría

AI Researcher

About

Machine Learning Researcher

BSc in Electrical Engineering with a focus on Computer Science and Networking and currently pursuing an MSc in Computer Science with a specialization in Machine Learning and Artificial Intelligence, I am a machine learning researcher with extensive experience in various domains. My research encompasses computer vision models, natural language processing (NLP), reinforcement learning, and knowledge graphs. I have developed and worked with deep learning models across diverse applications and conducted research on innovative techniques within these fields.

Experience

Education

May 2023 - Present

MSc in Computer Science - Costa Rica Institute of Technology

Extensive experience in deep learning, including the design and implementation of complex neural networks.
In-depth knowledge of data mining techniques for extracting valuable insights from large datasets.

Advanced skills in machine learning algorithms, model training, and evaluation.
Hands-on experience with various frameworks and tools for deep learning and data analysis.

Mar 2018 - Dec 2023

BSc in Electrical Engineering - University of Costa Rica

Extensive knowledge in low-level and embedded programming, including C programming and hardware acceleration. Computer and memory architectures.
Gained experience in high-level programming for machine learning and deep learning.
GPU programming, particularly using CUDA.

Profesional Experience

Oct 2024 - Present

AI Frameworks Engineer - Intel

Developed and optimized deep learning applications using frameworks such as PyTorch, TensorFlow, and ONNX Runtime, focusing on improving performance and efficiency for modern CPU/GPU ar- chitectures.
Conducted performance analysis, profiling, and optimization for deep learning models, achieving substantial gains in latency and throughput by implementing techniques like model compression, quantization, and graph compiler optimizations.
Utilized CUDA programming to accelerate key deep learning operations and kernels, optimizing for hardware architectures including Intel Xeon processors and GPUs.
Integrated Neural Architecture Search (NAS) techniques to enhance model performance, exploring hardware-aware optimizations for deep learning frameworks.

Aug 2023 - Oct 2024

Systems Software Engineer - Hewlett Packard Enterprise (HPE)

Extensive experience in low-level hardware and embedded programming using C.
Storage protocols such as SSDs, HDDs, flash memory, SATA, NVMe, SCSI, PCIe.
Proficient in bash scripting for Linux-based operating systems.
Developed Python scripts for automation tasks.
Worked with virtualization technologies, including Docker containers and Kubernetes.

April 2023 - Present

Postgraduate Researcher - Costa Rica Institute of Technology • Department of Computer Science

Researched techniques for hardware acceleration for deep learning applications on FPGAs.
Focused on model compression, quantization, and distillation.
Collaborated with undergraduate and postgraduate researchers from various fields.
Investigated reinforcement learning for generative AI in hardware synthesis.
Explored graph representation for hardware circuits.

Jul 2022 - Jul 2023

Analytics Engineer - Walmart Global Tech

Worked with supply chain data, including data analysis and data visualization.
Conducted A/B testing and exploratory data analysis (EDA).
Developed machine learning models (Gradient Boost, Bayesian Optimization, Isolation Forests, KNN).
Utilized Google Cloud Platform (GCP) services.
Queried data using SQL, BigQuery, and Presto.

Skills

Coding skills

Python 97%

C++ 90%

Bash 90%

Docker 90%

CUDA 85%

R 85%

Professional skills

Software development 95%

Researching95%

ML Pipelines maintanance95%

Debugging 90%

Hardware Accelereation 90%

Research Interests

Computer Vision

Computer vision techniques with a focus on object detection and image segmentation as applied to robotics. Key areas of exploration involve the development of low-latency inference models to enhance real-time performance and accuracy. Additionally, the research seeks to optimize computer vision models for on-device machine learning, aiming to improve their computational efficiency and adaptability in resource-constrained environments.

NLP

Enhancement of large language models (LLMs) through advanced transformer architectures to improve contextual understanding and generation in natural language processing (NLP). This research focuses on developing novel transformer variants that address limitations in current LLMs, such as scalability, efficiency, and interpretability. Optimization of transformer networks for handling long-range dependencies and fine-tuning techniques for domain-specific tasks. Explore the integration of hierarchical attention mechanisms and adaptive inference strategies to enhance model performance and reduce computational overhead.

Knowledge Graphs

Leverage of hyperknowledge graphs to enhance factual information generation and data augmentation for natural language processing (NLP) tasks. This involves exploring advanced graph structures to improve the richness and accuracy of data representation. Key areas include the application of transformers for node embeddings and completion, aiming to refine the semantic understanding and connectivity within knowledge graphs. Current research efforts are directed towards integrating hypergraphs with NLP models to advance the quality of information retrieval, reasoning, and context-aware data augmentation.

TinyRL

Enhancement of algorithmic efficiency and scalability. Key areas include the development of lightweight RL algorithms tailored for constrained environments, often referred to as TinyRL. This research explores novel techniques for optimizing RL models to perform effectively with limited computational resources. Current topics involve improving model efficiency through techniques such as model compression, quantization, and pruning, as well as advancing methods for efficient policy learning and reward signal design. Additionally, integrating RL with edge computing platforms for real-time decision-making and adaptive control represents a significant area of exploration.

Hardware Acceleration

Optimization of reinforcement learning (RL) algorithms through hardware acceleration, particularly for TinyRL applications in edge and embedded systems. Implementation of specialized hardware architectures, such as FPGAs and ASICs, to accelerate RL computations while maintaining low power consumption and minimal latency. Model quantization and pruning techniques. On-device learning and inference capabilities by integrating hardware acceleration with machine learning models.

Projects

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Sentiment Analysis - Distributed Training

English to Latex Translation

Ongoing Research

H-RAG aims to enhance LLMs by integrating hypergraphs: Current research focuses on constructing hypergraphs from knowledge bases, representing them computationally, and developing neural network architectures to process hypergraph data. By capturing complex relationships, H-RAG addresses LLMs' limitations in factual accuracy and reasoning. This approach holds promise for improving information retrieval and text generation through hypergraph-aware processes, ultimately leading to more reliable and informative AI systems.